1. Field of the Invention
The present invention relates to a power supply apparatus and an image forming apparatus, and more particularly, to a DC/DC converter.
2. Description of the Related Art
As disclosed in Japanese Patent Application Laid-Open No. 2013-219983, a DC/DC converter like that illustrated in FIG. 7 is an example of a related-art power supply apparatus. When an input voltage Vin is supplied to a switching element such as a field effect transistor (hereinafter referred to simply as “FET”), and the FET performs a switching operation, a pulse voltage is supplied to an inductor Ls. The pulse voltage supplied to the inductor Ls is converted into a DC voltage by the inductor Ls, a diode Ds, and a capacitor Cs, and an output voltage Vout is generated. FIGS. 8A to 8D illustrate operating waveforms of the DC/DC converter illustrated in FIG. 7. An on time ton and an off time toff of the FET of the DC/DC converter are represented by the following expression.
            t      on        ≅                                        2            ·                          L              s                        ·                          C              s                        ·            Δ                    ⁢                                          ⁢                      V            1                                                V                          i              ⁢                                                          ⁢              n                                -                      V            ref                                          t      off        ≅                                        2            ·                          L              s                        ·                          C              s                        ·            Δ                    ⁢                                          ⁢                      V            2                                    V          ref                    
Here, ΔV1 represents an increase in the voltage of a V+ terminal of a comparator Cmp by a positive feedback resistor Rc, and ΔV2 represents a decrease in the voltage of a V− terminal of the comparator Cmp by the positive feedback resistor Rc. In the following, ΔV1 and ΔV2 are referred to as threshold voltage change amounts of the comparator Cmp. Further, the details of FIG. 7 are described below.
A switching period Is and a switching frequency fs of the FET of the above-mentioned DC/DC converter are represented by the following expression using the above-mentioned on time ton and off time toff of the FET.
            T      s        ≅                  t        on            +              t        off              ≅                                                      2              ·                              L                s                            ·                              C                s                            ·              Δ                        ⁢                                                  ⁢                          V              1                                                          V                              i                ⁢                                                                  ⁢                n                                      -                          V              ref                                          +                                                  2              ·                              V                s                            ·                              C                s                            ·              Δ                        ⁢                                                  ⁢                          V              2                                            V            ref                                          f      s        ≅          1                        t          on                +                  t          off                    
Typically, a larger switching frequency fs enables the size of the inductor Ls and the capacitor Cs used by the DC/DC converter to be reduced. Therefore, increasing the switching frequency fs of the DC/DC converter is known to contribute to reducing costs and the size of the apparatus in which the DC/DC converter is mounted. The switching frequency fs can be increased by setting the threshold voltage change amounts ΔV1 and ΔV2 of the comparator Cmp to smaller values based on the expressions of the switching period Is and the switching frequency fs of the FET.
However, it is known that delay times tr and tf of an output signal with respect to an input signal of the comparator Cmp after the input voltage Vin has been input change based on an overdrive voltage Vod of the comparator Cmp. FIGS. 9A to 9C illustrate the response characteristics of a typical comparator. Note that, the details of FIGS. 9A to 9C are described below. As illustrated in FIGS. 9A to 9C, the output delay times tr and tf shorten when the overdrive voltage Vod is large, and conversely lengthen when the overdrive voltage Vod is small.
In the related-art DC/DC converter illustrated in FIG. 7, the threshold voltage change amounts ΔV1 and ΔV2 of the comparator Cmp correspond to the overdrive voltage Vod. As described above, the switching frequency fs can be increased by setting the threshold voltage change amounts ΔV1 and ΔV2 of the comparator Cmp to smaller values. However, when the response characteristics of the comparator Cmp are considered, setting the threshold voltage change amounts ΔV1 and ΔV2 of the comparator Cmp to smaller values in order to increase the switching frequency fs results in the overdrive voltage Vod decreasing. Further, as illustrated in FIGS. 9A to 9C, when the overdrive voltage Vod decreases, the output delay times tr and tf lengthen, and the switching frequency fs decreases. Thus, there has been a limit to how much the switching frequency fs in a power supply apparatus can be increased. Further, as described above, when the switching frequency fs cannot be increased, reduction in the size and costs of the inductor Ls and the capacitor Cs is inhibited.